As ultra-large-scale-integrated-circuits (ULSI) circuits are scaled to smaller dimensions, continued improvement in device drive current is necessary. In a metal-oxide-semiconductor (MOS) device, for example, drive current is determined, in part, by gate length, gate capacitance, and carrier mobility. At a given device size, improved device current can be obtained by increasing the carrier mobility.
A widely used technique to enhance carrier mobility includes forming a strained silicon channel region in an MOS transistor. Strain or stress in the silicon crystal lattice can enhance bulk electron and hole mobility through the lattice. The formation of a strained silicon region for fabrication of the transistor channel is a relatively straight forward way to improve device performance without introducing process scaling complexity.
A common practice used to create strain in a silicon lattice is to form a layer of material adjacent to the silicon channel region that has a lattice constant that differs from silicon. Both silicon germanium (SiGe) and silicon carbide (SiC) have been used in MOS device fabrication. Since the lattice constant of SiGe is larger than that of silicon, the lattice mismatch puts the silicon under tension and the charge carrier mobility increases though the strained silicon lattice. Similarly, the lattice constant of SiC differs from silicon, however, the type of strain created by SiC differs from that created by SiGe. Alloys such as SiGe create compressive strain in silicon, while SiC creates tensile strain in silicon. A bi-axial, in-plane tensile strain field can improve performance in N-type MOS devices, and compressive strain parallel to channel length direction can improve performance in P-type MOS devices.
Strain can also be applied by forming a strain-inducing layer, such as an etch-stop layer, on the gate electrode and the source and drain regions of an MOS device. Materials such as strained silicon nitride induce strain in the underlying silicon regions due to the compressive force of the silicon nitride layer on the underlying silicon. Highly strained silicon nitride layers have been used as etch stop layers or sidewall spacers to introduce strain in the channel regions of MOS transistors.
While both of the above methods have found application for creating strained silicon devices, these methods suffer from non-uniform stress fields across a device caused by localized differences component density. In particular, regions of a device having a high density population of device components, such as MOS transistors, exhibit lower drive current than MOS transistors in substrate regions having a lower transistor population density. For example, the effect of compressive strain from an etch-stop layer is much more pronounced on silicon regions having a low transistor density as compared to regions having relatively high transistor density.
FIG. 1(a) is a plot of on-current versus threshold saturation voltage for isolated verses densely populated transistors. FIG. 1(b) is a plot of off-current versus on-current for isolated verses densely populated transistors. The difference in the degree of stress applied by the etch stop layer results in a variance in electrical performance of these transistors by as much as 8 percent.
Shown in FIG. 2, in cross-section, are two regions of a semiconductor substrate 10 arranged in accordance with the prior art and populated with MOS transistors. A first region 12 of semiconductor substrate 10 includes gate electrodes 14 having a first lateral spacing D1. A second device region 18 includes gate electrodes 20 having a second lateral spacing D2. Gate electrodes 14 and 20 include sidewall spacers 22 on the vertical walls of the gate electrodes. The sidewall spacers can be formed, for example, by depositing a layer of spacer-forming material and anisotrophically etching the spacer-forming material.
In accordance with one of the strain-inducing methods described above, a compressive layer 24 is deposited to overlie the device structures in first region 12 and second region 18 of semiconductor substrate 10. Compressive layer 24 will enhance the electrical performance of the transistors by inducing strain in the channel regions of the transistors underlying the gate electrodes. The plots shown in FIGS. 1(a) and 1(b) are representative of the variance in transistor performance obtained by the MOS transistors shown in FIG. 2. In FIGS. 1(a) and 1(b), the plot identified as “Isolated” corresponds to transistors in first region 12 device, and the plot identified as “Dense” corresponds to the electrical performance of transistors in second region 18. As described above, the variance in electrical performance of the transistors in regions 12 and 18 of semiconductor substrate 10 is related to the non-uniform strain created in regions 12 and 18 by compressive layer 24.
Accordingly, a need exists to normalize the stress in device components of varying population density, so as to improve the performance uniformity of devices employing strained silicon technology.